The present invention relates to a very high stability clock synchronized on an external synchronization signal.
In a digital exchange, it is conventional to use a central time base which delivers signals to various units, thereby enabling the units to operate synchronously. A triplicated time base of this type is described in European patent number 0 129 098, for example. Time bases of this type are controlled by a clock signal provided by a synchronized clock. Such a synchronized clock receives a plurality of rate signals each recovered from a communications path such as a PCM link. By means of a digital phase lock loop, the clock latches onto a selected one of these rate signals. The servo-control loop includes a digital lowpass filter having a large time constant, of the order of several hours, for the purpose of eliminating any jitter that may be present in the selected rate signal.
Jitter is a frequency disturbance having a mean value of zero over a period of time corresponding substantially to the time constant of the filter. After selecting one of the rate signals, the synchronized clock provides a high accuracy signal only after a time delay that corresponds approximately to said time constant.
Thus, when the clock changes the rate signal used as the reference for its servo-control, a jump in frequency usually occurs, and either the clock is allowed to drift over the length of time required to bring it into synchronization with the new rate signal, which length of time is equivalent to the time constant of the filter, or else the time constant of the filter is temporarily shortened, in which case the jitter in the signal is also transmitted to the clock.
The object of the present invention is to provide a synchronized clock which does not have this drawback.